 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Single-Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier AD623 FEATURES Easy to use Higher performance than discrete design Single-supply and dual-supply operation Rail-to-rail output swing Input voltage range extends 150 mV below ground (single supply) Low power, 550 A maximum supply current Gain set with one external resistor Gain range: 1 (no resistor) to 1000 High accuracy dc performance 0.10% gain accuracy (G = 1) 0.35% gain accuracy (G > 1) 10 ppm maximum gain drift (G = 1) 200 V maximum input offset voltage (AD623A) 2 V/C maximum input offset drift (AD623A) 100 V maximum input offset voltage (AD623B) 1 V/C maximum input offset drift (AD623B) 25 nA maximum input bias current Noise: 35 nV/Hz RTI noise @ 1 kHz (G = 1) Excellent ac specifications 90 dB minimum CMRR (G = 10); 70 dB minimum CMRR (G = 1) at 60 Hz, 1 k source imbalance 800 kHz bandwidth (G = 1) 20 s settling time to 0.01% (G = 10) CONNECTION DIAGRAM -RG -IN +IN -VS AD623 1 2 3 4 8 7 6 5 +RG +VS OUTPUT REF 00778-001 TOP VIEW (Not to Scale) Figure 1. 8-Lead PDIP (N), SOIC (R), and MSOP (RM) Packages 120 110 100 90 CMR (dB) x1000 x100 80 70 x10 60 50 40 30 1 10 100 1k 10k 100k FREQUENCY (Hz) x1 Figure 2. CMR vs. Frequency, 5 VS, 0 VS APPLICATIONS Low power medical instrumentation Transducer interfaces Thermocouple amplifiers Industrial process controls Difference amplifiers Low power data acquisition GENERAL DESCRIPTION The AD623 is an integrated single-supply instrumentation amplifier that delivers rail-to-rail output swing on a 3 V to 12 V supply. The AD623 offers superior user flexibility by allowing single gain set resistor programming and by conforming to the 8-lead industry standard pinout configuration. With no external resistor, the AD623 is configured for unity gain (G = 1), and with an external resistor, the AD623 can be programmed for gains up to 1000. The AD623 holds errors to a minimum by providing superior ac CMRR that increases with increasing gain. Line noise, as well as line harmonics, are rejected because the CMRR remains constant up to 200 Hz. The AD623 has a wide input commonmode range and can amplify signals that have a common-mode voltage 150 mV below ground. Although the design of the AD623 was optimized to operate from a single supply, the AD623 still provides superior performance when operated from a dual voltage supply (2.5 V to 6.0 V). Low power consumption (1.5 mW at 3 V), wide supply voltage range, and rail-to-rail output swing make the AD623 ideal for battery-powered applications. The rail-to-rail output stage maximizes the dynamic range when operating from low supply voltages. The AD623 replaces discrete instrumentation amplifier designs and offers superior linearity, temperature stability, and reliability in a minimum of space. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)1997-2008 Analog Devices, Inc. All rights reserved. 00778-002 AD623 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Connection Diagram ....................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Single Supply ................................................................................. 3 Dual Supplies ................................................................................ 4 Both Dual and Single Supplies.................................................... 6 Absolute Maximum Ratings............................................................ 7 ESD Caution .................................................................................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 15 Applications Information .............................................................. 16 Basic Connection ....................................................................... 16 Gain Selection ............................................................................. 16 Reference Terminal .................................................................... 16 Input and Output Offset Voltage .............................................. 17 Input Protection ......................................................................... 17 RF Interference ........................................................................... 17 Grounding ................................................................................... 18 Input Differential and Common-Mode Range vs. Supply and Gain .............................................................................................. 20 Outline Dimensions ....................................................................... 22 Ordering Guide .......................................................................... 23 REVISION HISTORY 7/08--Rev. C to Rev. D Updated Format .................................................................. Universal Changes to Features Section and General Description Section . 1 Changes to Table 3 ............................................................................ 6 Changes to Figure 40 ...................................................................... 14 Changes to Theory of Operation Section .................................... 15 Changes to Figure 42 and Figure 43 ............................................. 16 Changes to Table 7 .......................................................................... 19 Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 23 9/99--Rev. B to Rev. C Rev. D | Page 2 of 24 AD623 SPECIFICATIONS SINGLE SUPPLY Typical @ 25C single supply, VS = 5 V, and RL = 10 k, unless otherwise noted. Table 1. Parameter GAIN Gain Range Gain Error 1 Conditions G= 1 + (100 k/RG) G1 VOUT = 0.05 V to 3.5 V G > 1 VOUT = 0.05 V to 4.5 V 0.03 0.10 0.10 0.10 G1 VOUT = 0.05 V to 3.5 V G > 1 VOUT = 0.05 V to 4.5 V 50 5 50 Total RTI error = VOSI + VOSO/G 25 0.1 200 2.5 200 350 2 1000 1500 10 200 0.1 500 2.5 500 650 2 2000 2600 10 25 0.1 200 2.5 100 160 1 500 1100 10 V V V/C V V V/C 10 50 5 50 10 50 5 50 10 ppm ppm/C ppm/C 0.10 0.35 0.35 0.35 0.03 0.10 0.10 0.10 0.10 0.35 0.35 0.35 0.03 0.10 0.10 0.10 0.05 0.35 0.35 0.35 % % % % Min AD623A Typ Max Min AD623ARM Typ Max Min AD623B Typ Max Unit 1 1000 1 1000 1 1000 G=1 G = 10 G = 100 G = 1000 Nonlinearity G = 1 to 1000 Gain vs. Temperature G=1 G > 11 VOLTAGE OFFSET Input Offset, VOSI Over Temperature Average Tempco Output Offset, VOSO Over Temperature Average Tempco Offset Referred to the Input vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature Average Tempco Input Offset Current Over Temperature Average Tempco 80 100 120 120 100 120 140 140 17 25 0.25 5 25 27.5 2 2.5 80 100 120 120 100 120 140 140 17 25 0.25 5 25 27.5 2 2.5 80 100 120 120 100 120 140 140 17 25 0.25 5 25 27.5 2 2.5 dB dB dB dB nA nA pA/C nA nA pA/C Rev. D | Page 3 of 24 AD623 Parameter INPUT Input Impedance Differential Common-Mode Input Voltage Range 2 Common-Mode Rejection at 60 Hz with 1 k Source Imbalance G=1 G = 10 G = 100 G = 1000 OUTPUT Output Swing Conditions Min AD623A Typ Max Min AD623ARM Typ Max Min AD623B Typ Max Unit 2||2 2||2 VS = 3 V to 12 V (-VS) - 0.15 (+VS) - 1.5 (-VS) - 0.15 2||2 2||2 (+VS) - 1.5 (-VS) - 0.15 2||2 2||2 (+VS) - 1.5 G||pF G||pF V VCM = 0 V to 3 V VCM = 0 V to 3 V VCM = 0 V to 3 V VCM = 0 V to 3 V RL = 10 k RL = 100 k 70 90 105 105 0.01 0.01 80 100 110 110 (+VS) - 0.5 (+VS) - 0.15 70 90 105 105 0.01 0.01 80 100 110 110 (+VS) - 0.5 (+VS) - 0.15 77 94 105 105 0.01 0.01 86 100 110 110 (+VS) - 0.5 (+VS) - 0.15 dB dB dB dB V V DYNAMIC RESPONSE Small Signal -3 dB Bandwidth G=1 G = 10 G = 100 G = 1000 Slew Rate Settling Time to 0.01% G=1 G = 10 1 2 800 100 10 2 0.3 VS = 5 V Step size: 3.5 V Step size: 4 V, VCM = 1.8 V 30 20 800 100 10 2 0.3 30 20 800 100 10 2 0.3 30 20 kHz kHz kHz kHz V/s s s Does not include effects of external resistor, RG. One input grounded. G = 1. DUAL SUPPLIES Typical @ 25C dual supply, VS = 5 V, and RL = 10 k, unless otherwise noted. Table 2. Parameter GAIN Gain Range Gain Error 1 Conditions G= 1 + (100 k/RG) G1 VOUT = -4.8 V to +3.5 V G > 1 VOUT = 0.05 V to 4.5 V 0.03 0.10 0.10 0.10 0.10 0.35 0.35 0.35 0.03 0.10 0.10 0.10 0.10 0.35 0.35 0.35 0.03 0.10 0.10 0.10 0.05 0.35 0.35 0.35 % % % % Min AD623A Typ Max AD623ARM Min Typ Max Min AD623B Typ Max Unit 1 1000 1 1000 1 1000 G=1 G = 10 G = 100 G = 1000 Rev. D | Page 4 of 24 AD623 Parameter Nonlinearity Conditions G1 VOUT = -4.8 V to +3.5 V G > 1 VOUT = -4.8 V to +4.5 V Min AD623A Typ Max Min AD623ARM Typ Max Min AD623B Typ Max Unit G = 1 to 1000 Gain vs. Temperature G=1 G > 11 VOLTAGE OFFSET Input Offset, VOSI Over Temperature Average Tempco Output Offset, VOSO Over Temperature Average Tempco Offset Referred to the Input vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature Average Tempco Input Offset Current Over Temperature Average Tempco INPUT Input Impedance Differential Common-Mode Input Voltage Range 2 Common-Mode Rejection at 60 Hz with 1 k Source Imbalance G=1 G = 10 G = 100 G = 1000 OUTPUT Output Swing 50 5 50 Total RTI error = VOSI + VOSO/G 25 0.1 200 2.5 200 350 2 1000 1500 10 10 50 5 50 10 50 5 50 10 ppm ppm/C ppm/C 200 0.1 500 2.5 500 650 2 2000 2600 10 25 0.1 200 2.5 100 160 1 500 1100 10 V V V/C V V V/C 80 100 120 120 100 120 140 140 17 25 0.25 5 25 27.5 2 2.5 80 100 120 120 100 120 140 140 17 25 0.25 5 25 27.5 2 2.5 80 100 120 120 100 120 140 140 17 25 0.25 5 25 27.5 2 2.5 dB dB dB dB nA nA pA/C nA nA pA/C 2||2 2||2 VS = +2.5 V to 6 V (-VS) - 0.15 (+VS) - 1.5 (-VS) - 0.15 2||2 2||2 (+VS) - 1.5 (-VS) - 0.15 2||2 2||2 (+VS) - 1.5 G||pF G||pF V VCM = +3.5 V to -5.15 V VCM = +3.5 V to -5.15 V VCM = +3.5 V to -5.15 V VCM = +3.5 V to -5.15 V RL = 10 k, VS = 5 V RL = 100 k 70 90 105 105 80 100 110 110 70 90 105 105 80 100 110 110 77 94 105 105 86 100 110 110 dB dB dB dB (-VS) + 0.2 (-VS) + 0.05 (+VS) - 0.5 (+VS) - 0.15 (-VS) + 0.2 (-VS) + 0.05 (+VS) - 0.5 (+VS) - 0.15 (-VS) + 0.2 (-VS) + 0.05 (+VS) - 0.5 (+VS) - 0.15 V V Rev. D | Page 5 of 24 AD623 Parameter DYNAMIC RESPONSE Small Signal -3 dB Bandwidth G=1 G = 10 G = 100 G = 1000 Slew Rate Settling Time to 0.01% G=1 G = 10 1 2 Conditions Min AD623A Typ Max Min AD623ARM Typ Max Min AD623B Typ Max Unit 800 100 10 2 0.3 VS = 5 V, 5 V step 30 20 800 100 10 2 0.3 800 100 10 2 0.3 kHz kHz kHz kHz V/s 30 20 30 20 s s Does not include effects of external resistor, RG. One input grounded. G = 1. BOTH DUAL AND SINGLE SUPPLIES Table 3. Parameter NOISE Voltage Noise, 1 kHz Conditions Total RTI noise = Min AD623A Typ Max Min AD623ARM Typ Max Min AD623B Typ Max Unit (eni )2 + (eno /G )2 Input, Voltage Noise, eni Output, Voltage Noise, eno RTI, 0.1 Hz to 10 Hz G=1 G = 1000 Current Noise 0.1 Hz to 10 Hz REFERENCE INPUT RIN IIN Voltage Range Gain to Output POWER SUPPLY Operating Range Quiescent Current Over Temperature TEMPERATURE RANGE For Specified Performance 35 50 3.0 1.5 100 1.5 100 20% 50 -VS 1 0.0002 Dual supply Single supply Dual supply Single supply 2.5 2.7 375 305 6 12 550 480 625 +85 2.5 2.7 375 305 35 50 3.0 1.5 100 1.5 100 20% 50 -VS 1 0.0002 6 12 550 480 625 +85 2.5 2.7 375 305 35 50 3.0 1.5 100 1.5 100 20% 50 -VS 1 0.0002 6 12 550 480 625 +85 nV/Hz nV/Hz V p-p V p-p fA/Hz pA p-p k 60 +VS A V V f = 1 kHz VIN+, VREF = 0 V 60 +VS 60 +VS V V A A A C -40 -40 -40 Rev. D | Page 6 of 24 AD623 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Supply Voltage Internal Power Dissipation 1 Differential Input Voltage Output Short-Circuit Duration Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) 1 Rating 6 V 650 mW 6 V Indefinite -65C to +125C -40C to +85C 300C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Specification is for device in free air: 8-Lead PDIP Package: JA = 95C/W 8-Lead SOIC Package: JA = 155C/W 8-Lead MSOP Package: JA = 200C/W. Rev. D | Page 7 of 24 AD623 TYPICAL PERFORMANCE CHARACTERISTICS At 25C, VS = 5 V, and RL = 10 k, unless otherwise noted. 300 280 260 240 220 200 UNITS 22 20 18 16 14 12 10 8 6 4 2 00778-003 180 UNITS 160 140 120 100 80 60 40 20 0 -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 -600 -500 -400 -300 -200 -100 0 100 200 300 400 500 INPUT OFFSET VOLTAGE (V) OUTPUT OFFSET VOLTAGE (V) Figure 3. Typical Distribution of Input Offset Voltage; Package Option N-8, R-8 Figure 6. Typical Distribution of Output Offset Voltage, VS = 5 V, Single Supply, VREF = -0.125 V; Package Option N-8, R-8 210 180 150 120 90 60 30 0 -0.245 -0.240 -0.235 -0.230 -0.225 -0.220 -0.215 -0.210 INPUT OFFSET CURRENT (nA) 480 420 360 300 UNITS 240 180 120 60 0 -800 -600 -400 -200 0 200 400 600 800 OUTPUT OFFSET VOLTAGE (V) UNITS 00778-004 Figure 4. Typical Distribution of Output Offset Voltage; Package Option N-8, R-8 Figure 7. Typical Distribution for Input Offset Current; Package Option N-8, R-8 20 18 16 14 12 UNITS 22 20 18 16 14 UNITS 12 10 8 6 4 2 00778-005 10 8 6 4 2 -80 -60 -40 -20 0 20 40 60 80 100 0 0.005 0.010 INPUT OFFSET VOLTAGE (V) INPUT OFFSET CURRENT (nA) Figure 5. Typical Distribution of Input Offset Voltage, VS = 5 V, Single Supply, VREF = -0.125 V; Package Option N-8, R-8 Figure 8. Typical Distribution for Input Offset Current, VS = 5 V, Single Supply, VREF = -0.125 V; Package Option N-8, R-8 Rev. D | Page 8 of 24 00778-008 0 0 -0.025 -0.020 -0.015 -0.010 -0.005 00778-007 00778-006 0 AD623 1600 1400 1200 1000 20 30 25 IBIAS (nA) 00778-009 UNITS 800 600 400 200 0 75 80 85 90 95 100 105 110 115 120 125 130 CMRR (dB) 15 10 5 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C) Figure 9. Typical Distribution for CMRR (G = 1) VOLTAGE NOISE SPECTRAL DENSITY (nV/ Hz RTI) 1k Figure 12. IBIAS vs. Temperature 1k CURRENT NOISE SPECTRAL DENSITY (fA/ Hz) 100 G=1 100 G= 10 G= 100 G= 1000 00778-010 1 10 100 1k 10k 100k 1 10 100 FREQUENCY (Hz) 1k FREQUENCY (Hz) Figure 10. Voltage Noise Spectral Density vs. Frequency 22 21 20 19 Figure 13. Current Noise Spectral Density vs. Frequency 20.0 19.5 19.0 18.5 IBIAS (nA) IBIAS (nA) 18 17 16 15 14 -4 -2 CMV (V) 0 2 4 18.0 17.5 17.0 16.5 16.0 -4 00778-011 -3 -2 -1 CMV (V) 0 1 2 Figure 11. IBIAS vs. CMV, VS = 5 V Figure 14. IBIAS vs. CMV, VS = 2.5 V Rev. D | Page 9 of 24 00778-014 00778-013 10 10 00778-012 0 -60 AD623 CH1 10mV A 1s 100mV VERT 120 110 100 90 x1000 CMR (dB) 80 x100 70 60 x10 50 x1 00778-015 40 30 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 15. 0.1 Hz to 10 Hz Current Noise (0.71 pA/DIV) 70 60 50 40 Figure 18. CMR vs. Frequency, 5 VS 1V/DIV 1s G = 1000 G = 100 GAIN (dB) 30 20 10 0 -10 G=1 G = 10 00778-016 -20 1k 10k FREQUENCY (Hz) 100k 1M 00778-019 00778-020 -30 100 Figure 16. 0.1 Hz to 10 Hz RTI Voltage Noise (1 DIV = 1 V p-p) 120 110 Figure 19. Gain vs. Frequency (VS = 5 V, 0 V), VREF = 2.5 V 5 4 VS = 5V MAXIMUM OUTPUT VOLTAGE (V) 100 90 x1000 x100 3 2 1 0 -1 -2 -3 -4 VS = 2.5V CMR (dB) 80 70 x10 60 50 40 30 1 10 100 1k 10k 100k FREQUENCY (Hz) x1 00778-017 -5 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 COMMON-MODE INPUT (V) Figure 17. CMR vs. Frequency, = 5 VS, 0 VS, VREF = 2.5 V Figure 20. Maximum Output Voltage vs. Common-Mode Input, G = 1, RL = 100 k Rev. D | Page 10 of 24 00778-018 AD623 5 4 VS = 5V VS = 2.5V 120 100 G = 100 80 60 G = 10 40 G=1 20 0 1 10 100 1k 10k 100k FREQUENCY (Hz) G = 1000 140 MAXIMUM OUTPUT VOLTAGE (V) 3 1 0 -1 -2 -3 -4 00778-021 -5 -4 -3 -2 -1 0 1 2 3 4 5 COMMON-MODE INPUT (V) Figure 21. Maximum Output Voltage vs. Common-Mode Input, G 10, RL = 100 5 140 120 4 100 Figure 24. Positive PSRR vs. Frequency, 5 VS MAXIMUM OUTPUT VOLTAGE (V) G = 1000 POSITIVE PSSR (dB) 3 G = 100 80 60 G = 10 40 G=1 20 2 1 00778-022 0 1 2 3 4 5 1 10 100 1k 10k 100k COMMON-MODE INPUT (V) FREQUENCY (Hz) Figure 22. Maximum Output Voltage vs. Common-Mode Input, G = 1, VS = 5 V, RL = 100 k 5 140 120 4 100 80 Figure 25. Positive PSRR vs. Frequency, 5 VS, 0 VS G = 1000 G = 100 MAXIMUM OUTPUT VOLTAGE (V) 3 NEGATIVE PSRR (dB) G = 10 60 G=1 40 20 2 1 00778-023 0 1 2 3 4 5 1 10 100 1k 10k 100k COMMON-MODE INPUT (V) FREQUENCY (Hz) Figure 23. Maximum Output Voltage vs. Common-Mode Input, G 10, VS = 5 V, RL = 100 k Figure 26. Negative PSRR vs. Frequency, 5 VS Rev. D | Page 11 of 24 00778-026 0 -1 0 00778-025 0 -1 0 00778-024 -5 -6 POSITIVE PSSR (dB) 2 AD623 10 500V 1V 10s 8 OUTPUT VOLTAGE (V p-p) 6 4 VS = 5V VS = 2.5V 2 00778-030 0 20 40 60 80 100 FREQUENCY (kHz) 00778-027 0 Figure 27. Large Signal Response, G 10 1k Figure 30. Large Signal Pulse Response and Settling Time, G = -10 (0.250 mV = 0.01%), CL = 100 pF 10mV 2V 50s SETTLING TIME (s) 100 10 1 10 GAIN (V/V) 100 1k Figure 28. Settling Time to 0.01% vs. Gain, for a 5 V Step at Output, CL = 100 pF, VS = 5 V 500V 1V 20s 00778-028 1 Figure 31. Large Signal Pulse Response and Settling Time, G = 100, CL = 100 pF 20mV 2V 500s 00778-029 Figure 29. Large Signal Pulse Response and Settling Time, G = -1 (0.250 mV = 0.01%), CL = 100 pF Figure 32. Large Signal Pulse Response and Settling Time, G = -1000 (5 mV = 0.01%), CL = 100 pF Rev. D | Page 12 of 24 00778-032 00778-031 AD623 20mV 2s 20mV 500s 00778-033 Figure 33. Small Signal Pulse Response, G = 1, RL = 10 k, CL = 100 pF Figure 36. Small Signal Pulse Response, G = 1000, RL = 10 k, CL = 100 pF 20mV 5s 200V 00778-034 1V Figure 34. Small Signal Pulse Response, G = 10, RL = 10 k, CL = 100 pF Figure 37. Gain Nonlinearity, G = -1 (50 ppm/DIV) 20mV 50s 20V 1V 00778-035 Figure 35. Small Signal Pulse Response, G = 100, RL = 10 k, CL = 100 pF Figure 38. Gain Nonlinearity, G = -10 (6 ppm/DIV) Rev. D | Page 13 of 24 00778-038 00778-037 00778-036 AD623 V+ 50V 1V (V+) -0.5 OUTPUT VOLTAGE SWING (V) 00778-039 (V+) -1.5 (V+) -2.5 (V-) +0.5 0 0.5 1.0 OUTPUT CURRENT (mA) 1.5 2.0 Figure 39. Gain Nonlinearity, G = -100, 15 ppm/DIV Figure 40. Output Voltage Swing vs. Output Current Rev. D | Page 14 of 24 00778-040 V- AD623 THEORY OF OPERATION The AD623 is an instrumentation amplifier based on a modified classic 3-op-amp approach, to assure single or dual supply operation even at common-mode voltages at the negative supply rail. Low voltage offsets, input and output, as well as absolute gain accuracy, and one external resistor to set the gain, make the AD623 one of the most versatile instrumentation amplifiers in its class. The input signal is applied to PNP transistors acting as voltage buffers and providing a common-mode signal to the input amplifiers (see Figure 41). An absolute value 50 k resistor in each amplifier feedback assures gain programmability. The differential output is 100 k VC VO = 1 + RG The differential voltage is then converted to a single-ended voltage using the output amplifier, which also rejects any common-mode signal at the output of the input amplifiers. Because the amplifiers can swing to either supply rail, as well as have their common-mode range extended to below the negative supply rail, the range over which the AD623 can operate is further enhanced (see Figure 20 and Figure 21). The output voltage at Pin 6 is measured with respect to the potential at Pin 5. The impedance of the reference pin is 100 k; therefore, in applications requiring V/I conversion, a small resistor between Pin 5 and Pin 6 is all that is needed. POSITIVE SUPPLY 7 INVERTING 2 4 1 50k 50k 50k GAIN 50k 7 50k 50k OTUPUT 6 REF 5 8 NONINVERTING 3 4 NEGATIVE SUPPLY 00778-041 Figure 41. Simplified Schematic Note that the bandwidth of the in-amp decreases as gain is increased. This occurs because the internal op-amps are the standard voltage feedback design. At unity gain, the output amplifier limits the bandwidth. Rev. D | Page 15 of 24 AD623 APPLICATIONS INFORMATION BASIC CONNECTION Figure 42 and Figure 43 show the basic connection circuits for the AD623. The +VS and -VS terminals are connected to the power supply. The supply can be either bipolar (VS = 2.5 V to 6 V) or single supply (-VS = 0 V, +VS = 3.0 V to 12 V). Power supplies should be capacitively decoupled close to the power pins of the device. For the best results, use surface-mount 0.1 F ceramic chip capacitors and 10 F electrolytic tantalum capacitors. +VS 0.1F 10F The input voltage, which can be either single-ended (tie either -IN or +IN to ground), or differential is amplified by the programmed gain. The output signal appears as the voltage difference between the OUTPUT pin and the externally applied voltage on the REF input. For a ground-referenced output, REF should be grounded. GAIN SELECTION The gain of the AD623 is resistor programmed by RG, or more precisely, by whatever impedance appears between Pin 1 and Pin 8. The AD623 is designed to offer accurate gains using 0.1% to 1% tolerance resistors. Table 5 shows the required values of RG for the various gains. Note that for G = 1, the RG terminals are unconnected (RG = ). For any arbitrary gain, RG can be calculated by RG = 100 k/(G - 1) +2.5V TO +6V RG OUTPUT RG REF VIN RG VOUT REF (INPUT) 0.1F -VS 10F 00778-042 REFERENCE TERMINAL The reference terminal potential defines the zero output voltage and is especially useful when the load does not share a precise ground with the rest of the system. It provides a direct means of injecting a precise offset to the output. The reference terminal is also useful when bipolar signals are being amplified because it can be used to provide a virtual ground voltage. The voltage on the reference terminal can be varied from -VS to +VS. -2.5V TO -6V Figure 42. Dual-Supply Basic Connection +VS 0.1F 10F +3V TO +12V RG OUTPUT RG REF VIN RG VOUT REF (INPUT) 00778-055 Figure 43. Single-Supply Basic Connection Table 5. Required Values of Gain Resistors Desired Gain 2 5 10 20 33 40 50 65 100 200 500 1000 1% Standard Table Value of RG () 100 k 24.9 k 11 k 5.23 k 3.09 k 2.55 k 2.05 k 1.58 k 1.02 k 499 200 100 Calculated Gain Using 1% Resistors 2 5.02 10.09 20.12 33.36 40.21 49.78 64.29 99.04 201.4 501 1001 Rev. D | Page 16 of 24 AD623 INPUT AND OUTPUT OFFSET VOLTAGE The low errors of the AD623 are attributed to two sources, input and output errors. The output error is divided by the programmed gain when referred to the input. In practice, the input errors dominate at high gains and the output errors dominate at low gains. The total VOS for a given gain is calculated as the following: Total Error RTI = Input Error + (Output Error/G) Total Error RTO = (Input Error x G) + Output Error the in-amp. Resistor R1 and Capacitor C1 (and likewise, R2 and C2) form a low-pass RC filter that has a -3 dB bandwidth equal to F = 1/(2 R1C1). Using the component values shown, this filter has a -3 dB bandwidth of approximately 40 kHz. Resistors R1 and R2 were selected to be large enough to isolate the input of the circuit from the capacitors, but not large enough to significantly increase the noise of the circuit. To preserve common-mode rejection in the amplifier's pass band, Capacitors C1 and C2 need to be 5% or better units, or low cost 20% units can be tested and binned to provide closely matched devices. +VS 0.33F R1 4.02k 1% C1 1000pF 5% RG 0.01F RTI offset errors and noise voltages for different gains are shown in Table 6. INPUT PROTECTION Internal supply referenced clamping diodes allow the input, reference, output, and gain terminals of the AD623 to safely withstand overvoltages of 0.3 V above or below the supplies. This is true for all gains and for power on and power off. This last case is particularly important because the signal source and amplifier may be powered separately. If the overvoltage is expected to exceed this value, the current through these diodes should be limited to about 10 mA using external current limiting resistors (see Figure 44). The size of this resistor is defined by the supply voltage and the required overvoltage protection. +VS I = 10mA MAX VOVER RLIM RLIM -VS RG RLIM = -IN +IN R2 C3 4.02k 0.047F 1% C2 1000pF 5% AD623 VOUT REFERENCE 0.33F 0.01F Figure 45. Circuit to Attenuate RF Interference AD623 OUTPUT VOVER -VS + 0.7V 00778-043 VOVER 10mA Figure 44. Input Protection RF INTERFERENCE All instrumentation amplifiers can rectify high frequency outof-band signals. Once rectified, these signals appear as dc offset errors at the output. The circuit in Figure 45 provides good RFI suppression without reducing performance within the pass band of Table 6. RTI Error Sources Gain 1 2 5 10 20 50 100 1000 Maximum Total Input Offset Error (V) AD623A AD623B 1200 600 700 350 400 200 300 150 250 125 220 110 210 105 200 100 Capacitor C3 is needed to maintain common-mode rejection at the low frequencies. R1/R2 and C1/C2 form a bridge circuit whose output appears across the input pins of the in-amp. Any mismatch between C1 and C2 unbalances the bridge and reduces the common-mode rejection. C3 ensures that any RF signals are common mode (the same on both in-amp inputs) and are not applied differentially. This second low-pass network, R1 + R2 and C3, has a -3 dB frequency equal to 1/(2 (R1 + R2) (C3)). Using a C3 value of 0.047 F, the -3 dB signal bandwidth of this circuit is approximately 400 Hz. The typical dc offset shift over frequency is less than 1.5 V and the circuit's RF signal rejection is better than 71 dB. The 3 dB signal bandwidth of this circuit may be increased to 900 Hz by reducing Resistors R1 and R2 to 2.2 k. The performance is similar to using 4 k resistors, except that the circuitry preceding the in-amp must drive a lower impedance load. Maximum Total Input Offset Drift (V/C) AD623A AD623B 12 11 7 6 4 3 3 2 2.5 1.5 2.2 1.2 2.1 1.1 2 1 Total Input Referred Noise (nV/Hz) AD623A and AD623B 62 45 38 35 35 35 35 35 Rev. D | Page 17 of 24 00778-044 +VS NOTES: 1. LOCATE C1 TO C3 AS CLOSE TO THE INPUT PINS AS POSSIBLE. AD623 The circuit in Figure 45 should be built using a PC board with a ground plane on both sides. All component leads should be as short as possible. Resistors R1 and R2 can be common 1% metal film units, but Capacitors C1 and C2 need to be 5% tolerance devices to avoid degrading the circuit's common-mode rejection. Either the traditional 5% silver mica units or Panasonic 2% PPS film capacitors are recommended. In many applications, shielded cables are used to minimize noise; for best CMR over frequency, the shield should be properly driven. Figure 46 shows an active guard driver that is configured to improve ac common-mode rejection by bootstrapping the capacitances of input cable shields, thus minimizing the capacitance mismatch between the inputs. +VS -IN RG 2 AD8031 RG 2 ground. The REF pin should, however, be tied to a low impedance point for optimal CMR. The use of ground planes is recommended to minimize the impedance of ground returns (and hence the size of dc errors). To isolate low level analog signals from a noisy digital environment, many data acquisition components have separate analog and digital ground returns (see Figure 47). All ground pins from mixed signal components, such as analog-to-digital converters (ADCs), should be returned through the high quality analog ground plane. Maximum isolation between analog and digital is achieved by connecting the ground planes back at the supplies. The digital return currents from the ADC that flow in the analog ground plane, in general, have a negligible effect on noise performance. If there is only a single power supply available, it must be shared by both digital and analog circuitry. Figure 48 shows how to minimize interference between the digital and analog circuitry. As in the previous case, separate analog and digital ground planes should be used (reasonably thick traces can be used as an alternative to a digital ground plane). These ground planes should be connected at the ground pin of the power supply. Separate traces should be run from the power supply to the supply pins of the digital and analog circuits. Ideally, each device should have its own power supply trace, but these can be shared by a number of devices, as long as a single trace is not used to route current to both digital and analog circuitry. 2 1 7 100 AD623 8 3 4 5 6 OUTPUT REF 00778-045 +IN -VS Figure 46. Common-Mode Shield Driver GROUNDING Because the AD623 output voltage is developed with respect to the potential on the reference terminal, many grounding problems can be solved by simply tying the REF pin to the appropriate local ANALOG POWER SUPPLY +5V -5V GND DIGITAL POWER SUPPLY GND +5V 0.1F 0.1F 0.1F 0.1F 2 7 1 4 6 6 14 AD623 3 5 VDD 4 VIN1 3 AGND DGND 12 AGND VDD Figure 47. Optimal Grounding Practice for a Bipolar Supply Environment with Separate Analog and Digital Supplies POWER SUPPLY +5V GND 0.1F 0.1F 0.1F 2 7 1 4 6 6 14 AD623 3 5 VDD 4 VIN1 AGND DGND 12 AGND VDD Figure 48. Optimal Ground Practice in a Single Supply Environment Rev. D | Page 18 of 24 00778-047 AD7892-2 ADC MICROPROCESSOR 00778-046 VIN2 AD7892-2 ADC MICROPROCESSOR AD623 Ground Returns for Input Bias Currents Input bias currents are those dc currents that must flow to bias the input transistors of an amplifier. These are usually transistor base currents. When amplifying floating input sources, such as transformers or ac-coupled sources, there must be a direct dc path into each input in order that the bias current can flow. Figure 49, Figure 50, and Figure 51 show how a bias current path can be provided for the cases of transformer coupling, thermocouple, and capacitive ac coupling. In dc-coupled resistive bridge applications, providing this path is generally not necessary as the bias current simply flows from the bridge supply through the bridge into the amplifier. However, if the impedances that the two inputs see are large and differ by a large amount (>10 k), the offset current of the input stage causes dc errors proportional with the input offset voltage of the amplifier. +VS -IN 2 1 7 Output Buffering The AD623 is designed to drive loads of 10 k or greater. If the load is less than this value, the output of the AD623 should be buffered with a precision single-supply op amp, such as the OP113. This op amp can swing from 0 V to 4 V on its output while driving a load as small as 600 . Table 7 summarizes the performance of some buffer op amps. 5V 0.1F 5V 0.1F VIN RG AD623 OP113 REFERENCE VOUT 00778-051 Figure 52. Output Buffering Table 7. Buffering Options AD623 6 5 4 RG 8 OUTPUT Op Amp OP113 OP191 Description Single supply, high output current Rail-to-rail input and output, low supply current +IN 3 REF LOAD 00778-048 -VS TO POWER SUPPLY GROUND Single-Supply Data Acquisition System Interfacing bipolar signals to single-supply ADCs presents a challenge. The bipolar signal must be mapped into the input range of the ADC. Figure 53 shows how this translation can be achieved. 5V 5V 5V 0.1F 0.1F Figure 49. Ground Returns for Bias Currents with Transformer-Coupled Inputs +VS -IN 2 1 7 RG 8 AD623 5 4 3 6 OTUPUT REF LOAD 00778-049 +IN 10mV TO POWER SUPPLY GROUND RG 1.02k AD623 REFERENCE AIN AD7776 -VS REFOUT REFIN 00778-052 Figure 50. Ground Returns for Bias Currents with Thermocouple Inputs +VS -IN 2 1 7 Figure 53. A Single-Supply Data Acquisition System RG 8 AD623 5 4 3 6 OUTPUT REF LOAD 00778-050 +IN 100k 100k -VS TO POWER SUPPLY GROUND Figure 51. Ground Returns for Bias Currents with AC-Coupled Inputs The bridge circuit is excited by a 5 V supply. The full-scale output voltage from the bridge (10 mV) therefore has a commonmode level of 2.5 V. The AD623 removes the common-mode component and amplifies the input signal by a factor of 100 (RGAIN = 1.02 k). This results in an output signal of 1 V. To prevent this signal from running into the ground rail of the AD623, the voltage on the REF pin must be raised to at least 1 V. In this example, the 2 V reference voltage from the AD7776 ADC is used to bias the output voltage of the AD623 to 2 V 1 V. This corresponds to the input range of the ADC. Rev. D | Page 19 of 24 AD623 Amplifying Signals with Low Common-Mode Voltage Because the common-mode input range of the AD623 extends 0.1 V below ground, it is possible to measure small differential signals which have low, or no, common-mode component. Figure 54 shows a thermocouple application where one side of the J-type thermocouple is grounded. 5V 0.1F the previous equations, the maximum and minimum input common-mode voltages are given by the following equations: VCMMAX = V+ - 0.7 V - VDIFF x Gain/2 VCMMIN = V- - 0.590 V + VDIFF x Gain/2 J-TYPE THERMOCOUPLE RG 1.02k These equations can be rearranged to give the maximum possible differential voltage (positive or negative) for a particular common-mode voltage, gain, and power supply. Because the signals on A1 and A2 can clip on either rail, the maximum differential voltage are the lesser of the two equations. |VDIFFMAX| = 2 (V+ - 0.7 V - VCM/Gain |VDIFFMAX| = 2 (VCM - V- +0.590 V/Gain However, the range on the differential input voltage range is also constrained by the output swing. Therefore, the range of VDIFF may have to be lower according the following equation. Input Range Available Output Swing/Gain AD623 REF OUTPUT Figure 54. Amplifying Bipolar Signals with Low Common-Mode Voltage Over a temperature range of -200C to +200C, the J-type thermocouple delivers a voltage ranging from -7.890 mV to +10.777 mV. A programmed gain on the AD623 of 100 (RG = 1.02 k) and a voltage on the REF pin of 2 V, results in the output voltage ranging from 1.110 V to 3.077 V relative to ground. 00778-053 2V INPUT DIFFERENTIAL AND COMMON-MODE RANGE vs. SUPPLY AND GAIN Figure 55 shows a simplified block diagram of the AD623. The voltages at the outputs of Amplifier A1 and Amplifier A2 are given by VA2 = VCM + VDIFF/2 + 0.6 V + VDIFF x RF/RG = VCM + 0.6 V + VDIFF x Gain/2 VA1 = VCM + VDIFF/2 + 0.6 V + VDIFF x RF/RG = VCM + 0.6 V - VDIFF x Gain/2 POSITIVE SUPPLY 7 For a bipolar input voltage with a common-mode voltage that is roughly half way between the rails, VDIFFMAX is half the value that the previous equations yield because the REF pin is at midsupply. Note that the available output swing is given for different supply conditions in the Specifications section. The equations can be rearranged to give the maximum gain for a fixed set of input conditions. Again, the maximum gain will be the lesser of the two equations. GainMAX = 2 (V+ - 0.7 V - VCM)/VDIFF GainMAX = 2 (VCM - V- +0.590 V)/VDIFF Again, it is recommended that the resulting gain times the input range is less than the available output swing. If this is not the case, the maximum gain is given by GainMAX = Available Output Swing/Input Range INVERTING 2 4 1 A1 RF 50k 50k 50k VDIFF 2 - + Also for bipolar inputs (that is, input range = 2 VDIFF), the maximum gain is half the value yielded by the previous equations because the REF pin must be at midsupply. OUTPUT 6 REF 5 VCM GAIN RG 8 VDIFF 2+ - A3 RF 50k 50k 50k The maximum gain and resulting output swing for different input conditions is given in Table 8. Output voltages are referenced to the voltage on the REF pin. For the purposes of computation, it is necessary to break down the input voltage into its differential and common-mode component. Therefore, when one of the inputs is grounded or at a fixed voltage, the common-mode voltage changes as the differential voltage changes. Take the case of the thermocouple amplifier in Figure 54. The inverting input on the AD623 is grounded; therefore, when the input voltage is -10 mV, the voltage on the noninverting input is -10 mV. For the purpose of the signal swing calculations, this input voltage should be composed of a commonmode voltage of -5 mV (that is, (+IN + -IN)/2) and a differential input voltage of -10 mV (that is, +IN - -IN). 7 A2 Figure 55. Simplified Block Diagram The voltages on these internal nodes are critical in determining whether the output voltage will be clipped. The VA1 and VA2 voltages can swing from approximately 10 mV above the negative supply (V- or ground) to within approximately 100 mV of the positive rail before clipping occurs. Based on this and from Rev. D | Page 20 of 24 00778-054 NONINVERTING 3 4 NEGATIVE SUPPLY AD623 Table 8. Maximum Attainable Gain and Resulting Output Swing for Different Input Conditions VCM (V) 0 0 0 0 0 2.5 2.5 2.5 1.5 1.5 0 0 VDIFF (V) 10 m 100 m 10 m 100 m 1 10 m 100 m 1 10 m 100 m 10 m 100 m REF Pin (V) 2.5 2.5 0 0 0 2.5 2.5 2.5 1.5 1.5 1.5 1.5 Supply Voltages (V) +5 +5 5 5 5 +5 +5 +5 +3 +3 +3 +3 Maximum Gain 118 11.8 490 49 4.9 242 24.2 2.42 142 14.2 118 11.8 Closest 1% Gain Resistor () 866 9.31 k 205 2.1 k 26.1 k 422 4.32 k 71.5 k 715 7.68 k 866 9.31 k Resulting Gain 116 11.7 488 48.61 4.83 238 24.1 2.4 141 14 116 11.74 Output Swing (V) 1.2 1.1 4.8 4.8 4.8 2.3 2.4 2.4 1.4 1.4 1.1 1.1 Rev. D | Page 21 of 24 AD623 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 1 5 4 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) BSC 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) MIN SEATING PLANE 0.005 (0.13) MIN 0.015 (0.38) GAUGE PLANE 0.430 (10.92) MAX 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 56. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 8 1 5 4 6.20 (0.2441) 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 45 0.51 (0.0201) 0.31 (0.0122) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 57. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. D | Page 22 of 24 012407-A 070606-A AD623 3.20 3.00 2.80 3.20 3.00 2.80 PIN 1 8 5 1 5.15 4.90 4.65 4 0.65 BSC 0.95 0.85 0.75 0.15 0.00 0.38 0.22 SEATING PLANE 1.10 MAX 8 0 0.80 0.60 0.40 0.23 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 58. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model AD623AN AD623ANZ 1 AD623AR AD623AR-REEL AD623AR-REEL7 AD623ARZ1 AD623ARZ-R71 AD623ARZ-RL1 AD623ARM AD623ARM-REEL AD623ARM-REEL7 AD623ARMZ1 AD623ARMZ-REEL1 AD623ARMZ-REEL71 AD623BN AD623BNZ1 AD623BR AD623BR-REEL AD623BR-REEL7 AD623BRZ1 AD623BRZ-R71 AD623BRZ-RL1 EVAL-INAMP-62RZ1 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel 8-Lead SOIC, 13" Tape and Reel 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP], 13" Tape and Reel 8-Lead Mini Small Outline Package [MSOP], 7" Tape and Reel 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP], 13" Tape and Reel 8-Lead Mini Small Outline Package [MSOP], 7" Tape and Reel 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel Evaluation Board Package Option N-8 N-8 R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 N-8 N-8 R-8 R-8 R-8 R-8 R-8 R-8 Branding J0A J0A J0A J0A J0A J0A Z = RoHS Compliant Part. Rev. D | Page 23 of 24 AD623 NOTES (c)1997-2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00788-0-7/08(D) Rev. D | Page 24 of 24 |
Price & Availability of AD623BR-REEL
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |